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📘 How RAM Works

DRAM is the computer's fast, rewriteable working memory — dense cells that must be refreshed because stored charge leaks away.

6
lessons
~30 min
to learn
Adults
level
Start the course →

What you’ll learn

  1. A tiny charge becomes a bitExplain how a DRAM cell stores a bit and how rows and columns address an array.A transistor selects a capacitor, and decoders turn an address into row and column choices.
  2. Reading a cell changes itTrace charge sharing, sensing, restoration, row buffers, and row hits.A DRAM read amplifies a tiny voltage difference and restores the disturbed cell.
  3. Charge leaks, so refresh runsExplain leakage, refresh intervals, and refresh costs.DRAM is dynamic because stored charge fades, so refresh continually restores rows.
  4. Bandwidth is not latencyDistinguish transfer bandwidth from request latency and describe controller scheduling.Open rows, banks, bursts, and controller decisions determine how quickly a request is served.
  5. Why caches matterContrast DRAM and SRAM and explain why caches hide DRAM latency.Dense DRAM supplies capacity while faster SRAM caches exploit locality near the processor.
  6. Putting a RAM access togetherCombine cell physics, refresh, scheduling, and hierarchy into one mental model.Responsive memory is a system-level result built on fragile capacitor cells and layers of control.

Questions this course answers

What are the two core storage elements in a classic DRAM cell?

The transistor selects the cell, while the capacitor holds the charge that represents its stored state.

Put a simplified DRAM read in order.

A row is opened, its tiny charge changes the bit line, the sense amplifier decides the value, and the result is written back.

Match each term with its role.

These terms describe different parts of the memory system: row state, maintenance, technology choice, and transfer capacity.

Why does a computer use both DRAM and SRAM?

The memory hierarchy uses each technology where its tradeoff fits: large working memory in DRAM and small speed-critical caches in SRAM.

Grounded in trusted sources

  • Samsung Semiconductor, DRAM glossary and memory overview: https://semiconductor.samsung.com/support/tools-resources/dictionary/semiconductor-glossary-dram/
  • Micron Technology, How DRAM memory works: https://www.micron.com/educatorhub/courses/how-dram-memory-works
  • Computer History Museum, Semiconductor Memory: Fast, Cheap, or Dense?: https://www.computerhistory.org/revolution/memory-storage/8/311
  • Arm, Exploring how cache coherency accelerates heterogeneous compute: https://developer.arm.com/community/arm-community-blogs/b/architectures-and-processors-blog/posts/exploring-how-cache-coherency-accelerates-heterogeneous-compute
  • Wikimedia Commons MediaWiki API image records: https://commons.wikimedia.org/w/api.php

Every Wunder lesson is built from real, reputable sources — never invented.

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