🔲 From Transistor to CPU: How Computers Compute

What you’ll learn

1. The Only TrickGrasp the single idea the entire course is built from — that a transistor is a switch whose output can operate the next switch — and understand why digital computing deliberately discards the transistor's analogue abilities.A light switch cannot throw another light switch, because its output (light) is a different kind of thing from its input (a finger). A transistor is operated by voltage and outputs voltage, so the chain continues without a human — that closure is the only genuinely new idea in the subject, and everything above it is arrangement. Used in its middle range a transistor amplifies smoothly, but analogue signals accumulate noise forever because noise is indistinguishable from signal. Used at its extremes it is merely a switch with two widely separated legal values, which lets every stage discard noise and re-emit a clean full-strength value. Computing chose the crude option deliberately.
2. The Inverter Is the AtomBuild a CMOS inverter and NAND gate from complementary transistors, and understand why CMOS burns power when it switches rather than when it holds — the fact that returns as the power wall.CMOS pairs an NMOS transistor that conducts on a high input with a PMOS that conducts on a low one, stacked so exactly one path is ever open: never both power and ground fighting over the output. Two transistors give an inverter; two NMOS in series with two PMOS in parallel give NAND in four. Plain AND cannot be built directly, because the complementary structure inherently inverts — it costs a NAND plus an inverter, six transistors, making NAND the cheaper native gate and inverting the textbook intuition. An idle CMOS gate passes almost no current; it costs energy only when it switches, so chip power scales roughly with gate count times clock frequency.
3. Why NAND Is EnoughProve NAND's functional completeness by constructing NOT, AND and OR from it, and understand why that property ends the search for new hardware primitives.Tie both NAND inputs together and you have NOT; invert a NAND's output and you have AND; invert both inputs before NANDing them and De Morgan's laws give you OR. From NOT, AND and OR every Boolean function that will ever be defined can be built — so a designer facing an instruction nobody has yet imagined never has to ask whether the hardware can express it, only how many gates and how deep. It also makes chips manufacturable, since a library reducible to a few endlessly repeated standard cells can be optimised obsessively and stamped out. It is the last new idea in the course; everything after is arrangement.
4. Arithmetic Falls Out of LogicDerive binary addition from logic gates, understand carry propagation as the origin of the critical path, and see two's complement as the representation trick that lets an adder subtract.Write out the four cases of adding two bits and addition is already present in the gates: the sum bit is XOR and the carry bit is AND. That circuit is a half adder; adding a carry-in makes a full adder, and chaining 64 of them makes a 64-bit adder. But the carry must ripple from bit 0 to bit 63 one gate delay at a time, giving the longest chain of gates any signal must cross — the critical path — which carry-lookahead buys back by spending silicon on parallel logic. Subtraction needs no subtractor at all: encode negatives in two's complement and the overflow bit falls off the end of the register, so the same adder gives the right answer without ever knowing the numbers were negative.
5. Memory Is a Circle of SwitchesUnderstand memory as feedback — an output wired back to an input — and grasp why SRAM and DRAM represent opposite bargains between speed and density.Combinational circuits have no past; wire an output back to an input and two inverters in a ring hold a stable value indefinitely, remembering by continuously re-convincing themselves. Dressed up for writing, that ring is an SRAM cell: fast, actively driven, and about six transistors per bit — which is why there is so little of it. DRAM instead stores each bit as charge on a tiny capacitor behind one transistor, giving the density for gigabytes, but the charge leaks within milliseconds so dedicated circuitry must refresh every row thousands of times a second, and reading is destructive and slow because a faint charge must be dumped onto a long wire and sensed. Registers are the fastest tier of all, wired directly into the execution machinery — and a CPU cannot compute on values in memory, it must load them first.
6. The Clock Is a Promise, Not a SpeedReframe the clock as a correctness guarantee rather than a speed, and understand the critical path as the physical quantity that sets clock frequency.Gates do not respond instantly and glitch through wrong values as their inputs arrive at different moments, so a circuit's output pins show plausible-looking garbage while it settles — and the circuit never announces that it is finished. A clock solves this crudely: between ticks the logic may thrash unobserved, and on each tick every register simultaneously captures whatever its input shows. The clock therefore isn't a speed but a promise that the slowest chain of gates on the die has settled before anyone looks. A 3.5 GHz rating asserts that the critical path settles in under about 286 picoseconds; tick sooner and half-computed values become official state, which is why overclocking failures produce confident wrong answers. Because the clock is global, one slow path anywhere holds back every circuit that finished early.
7. Fetch, Decode, ExecuteAssemble the CPU as a state machine running fetch-decode-execute, and close the gap between electricity and software by seeing a machine instruction as a bit pattern that opens gates.The stored-program idea puts the program in memory as numbers alongside its data, which is what allows a program to read, write and generate another program. The CPU loops: fetch the instruction at the address in the program counter, decode its bits through combinational logic that switches control lines, and execute by letting the selected registers flow through the ALU to the selected destination. The decoder is the step people expect to be magical and is the least magical — it is only gates. So a machine instruction is not a command the processor chooses to obey; it is a number whose bits physically open a particular set of paths. Machine code is a wiring diagram delivered one pattern at a time, and that is the entire gap between electricity and software.
8. The Assembly LineUnderstand pipelining as a throughput rather than latency improvement, and see branch prediction and speculative execution as the necessary answer to control hazards.In a naive fetch-decode-execute machine roughly two-thirds of the silicon idles at any moment, and the clock must accommodate the slowest stage. Pipelining overlaps stages like a car assembly line, so throughput rises several-fold on the same silicon — while the latency of any single instruction is unchanged or slightly worse. The costs are hazards: data hazards, where an instruction needs a result still in flight, answered by forwarding or stalling; and control hazards, where a branch cannot be resolved before the next fetch is needed. Since branches are roughly one instruction in five, deep pipelines cannot afford to stall, so processors guess with branch predictors that are right well over 95% of the time and execute speculatively, flushing on a miss. Speculation's lingering cache traces are the seam Spectre and Meltdown opened in 2018.
9. Memory Is the Real BottleneckUnderstand the memory wall as the defining constraint of modern architecture, and see caches as a bet on temporal and spatial locality that reaches up into the code you write.A CPU executes an instruction in well under a nanosecond, while a DRAM access is widely cited at roughly 50–100 ns — on the order of 150–400 cycles at a few GHz. The gap is structural, because DRAM's one-transistor leaky-capacitor cell is physically slow to sense in a way shrinking does not fix, and it widened every year for decades: the memory wall. Caches answer it with small fast SRAM and two bets about real programs — temporal locality (recently used things get reused) and spatial locality (neighbours get used, so fetch a whole 64-byte line). The hierarchy runs registers, L1 (roughly 1–5 cycles), L2 (roughly 10–15), L3 (roughly 30–50, shared), then DRAM. This is why walking an array can be many times faster than walking a linked list of the same values, though both are O(n) and Big-O cannot see the difference.
10. The Wall That Ended the Gigahertz RaceExplain why clock speeds stalled near 4 GHz around 2005 as the breakdown of Dennard scaling rather than of Moore's Law, and consolidate the whole tower as arrangement rather than accumulated new ideas.Robert Dennard's 1974 scaling law held that shrinking transistors could scale their voltage down too, keeping power density constant — so each generation delivered more transistors, a higher clock, and no extra heat, for free. It broke down around 2005–2007 because operating voltage could no longer be scaled: threshold voltage does not scale obligingly, and pushing further causes leakage, current bled continuously by transistors that never fully switch off. Power density rose, the silicon became uncoolable, and frequency stalled near 4 GHz, where it has essentially remained. Intel's NetBurst architecture had been built around clocks projected toward 10 GHz that never arrived. The industry went multicore — which, unlike a faster clock, speeds up nothing unless software is rewritten, and that is the origin of two decades of concurrency work.

Questions this course answers

Grounded in trusted sources

• Wikipedia — Dennard scaling — https://en.wikipedia.org/wiki/Dennard_scaling
• Wikipedia — CPU cache — https://en.wikipedia.org/wiki/CPU_cache
• Wikipedia — Cache hierarchy — https://en.wikipedia.org/wiki/Cache_hierarchy
• Rambus — Understanding Dennard scaling — https://www.rambus.com/blogs/understanding-dennard-scaling-2/
• Electronic Design — The Memory Wall Is Ending Multicore Scaling — https://www.electronicdesign.com/technologies/analog/article/21794572/the-memory-wall-is-ending-multicore-scaling
• Clayton Cafiero, University of Vermont — Memory hierarchy — https://www.uvm.edu/~cbcafier/cs2210/content/07_memory_hierarchy/memory_hierarchy.html
• Medium (Kushan Tharaka) — The Power Problem: Why Clock Speeds Stopped Increasing and What Came Next — https://medium.com/@kushanpeiris1118/the-power-problem-why-clock-speeds-stopped-increasing-and-what-came-next-a4973613e0b3

Every Wunder lesson is built from real, reputable sources — never invented.

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